1. Field of the Invention
This invention relates to a one-chip processor, and more particularly to a RISC (reduced instruction set computer) processor which efficiently supplies instructions.
2. Description of the Related Art
In general, a conventional microprocessor sequentially executes instructions. The conventional microprocessor is disadvantageous for the following reason: since the number of cycle (CPI: cycle per instruction) required for executing an instruction cannot be less than 1.0, it is impossible to improve the MIPS (million instruction per second) value, which indicates the performance of the microprocessor. Hence, in recent years, a Superscalar system or a VLIW (very long instruction word) system have been developed to decrease the CPI value, thereby improving the MIPS value. These methods are applied to, for example, a RISC processor, which has been developed and put to practical use. The RISC processor includes a plurality of pipe lines and executes instructions in parallel, thereby efficiently supplying instructions.
In the microprocessor of the Superscalar system, an instruction cache unit outputs instructions in parallel. The instructions are supplied to a plurality of instruction executing sections, such as an integer processor unit (IU) and a floating-point processor unit (FPU), and executed in parallel. However, in a conventional microprocessor of the Superscalar system, instructions are output in parallel from an instruction cache unit to instruction executing sections, and the instruction cache unit must output instructions of the same number as the instruction execution sections. Therefore, instructions cannot be efficiently supplied to executing sections.